The present invention relates to a solid-state image sensor having an improved performance with a higher charge well capacity which results in a higher dynamic range (DR) and a better signal to noise ratio (SNR), and more particularly to a complementary metal oxide semiconductor (CMOS) image sensor.
A typical pixel of the CMOS image sensor includes a photodiode, more precisely a pinned photodiode, and four transistors. The photodiode collects a photo-generated charge that is later transferred at a suitable moment by a charge transfer transistor onto a floating diffusion (FD) node which detects the charge. Prior to the charge transfer, however, the FD node must be first reset by a reset transistor to a suitable reference voltage, which is usually a terminal bias voltage, Vdd, or a bias close to this level. The reset causes kTC noise, which is normally added to a signal appearing on the FD node. Thus, it is necessary to read a voltage on the FD node twice, before and after the charge transfer. This operation is called a correlated double sampling (CDS) procedure and the CDS procedure allows sensing of only the voltage difference of the FD node caused by the charge transferred from the photodiode. A source follower (SF) transistor with a gate connected to the FD node, one terminal connected to the Vdd and the other terminal connected to a common column sense line via an addressing transistor performs sensing of the voltage on the FD node. For this reason, it is necessary to incorporate the four transistors in each pixel of a standard CMOS image sensor. The four transistors (4T) pixel circuit with the pinned photodiode is proposed in U.S. Pat. No. 5,625,210 issued to Lee, entitled “Active Pixel Sensor Integrated with a Pinned Photodiode”.
In modern CMOS sensor designs, circuits where several photodiodes may be shared are used as can be found for an example in U.S. Pat. No. 6,657,665B1 issued to Guidash, entitled “Active Pixel Sensor with Wired Floating Diffusions and Shared Amplifier”. In this patent, a dual pixel includes two photodiodes located in the neighboring rows of a sensor image array that share the same circuit. The shared photodiode concept can result in having only two metal bus lines in the row direction and two metal bus lines in the column direction per photodiode as shown in FIG. 1. The shared photodiode concept is very useful for designing small pixels since spacing and width of the metal lines determine a minimum pixel size. The operation of the shared photodiode pixel circuit can be easily understood from a simplified schematic diagram of the circuit 100 shown in FIG. 1. Two photodiodes 101 and 102 are connected through the respective charge transfer transistors 103 and 104 to a FD node 114 which detects charge. The FD node 114 is reset by a reset transistor 105 to a voltage level appearing on a Vdd node 108. The Vdd node 108 is connected to a column Vdd bus line 115. Gates of the charge transfer transistors 103 and 104 are biased through the respective horizontal bus lines 110 and 111, and a gate of the reset transistor 105 is biased through a horizontal bus line 109. A gate control signal Tx1 of the charge transfer transistor 103 is transferred through the horizontal bus line 110, and a gate control signal Tx2 of the charge transfer transistor 104 is transferred through the horizontal bus line 111. Also, a gate control signal Rx of the reset transistor 105 is transferred through the horizontal bus line 109. The FD node 114 is connected to a gate of a source follower (SF) transistor 106 that senses a voltage on the FD node 114. A terminal of the SF transistor 106 is connected to the Vdd node 108, thereby being connected to the Vdd column bus line 115. An output of the SF transistor 106 is connected through an addressing transistor 107 to a common column sense line 113. A horizontal bus line 112 controls a bias of the addressing transistor 107. A gate control signal Sx of the addressing transistor 107 is transferred through the horizontal bus line 112. As shown in FIG. 1, there are only two vertical (column) lines, the Vdd bus line 115 and a column sense line 113. There are also only two horizontal lines per photo site.
In order to better understand the operation of the 4T pixel, FIG. 2 illustrates a cross-sectional view of a simplified device. The simplified device 200 includes a single pinned photodiode 205, and a charge transfer transistor and a reset transistor corresponding to the photodiode 205. A source follower (SF) transistor 201 and an addressing transistor 202 are shown only schematically including connections of the SF transistor 201 and the addressing transistor 202 to the corresponding circuit nodes. A terminal of the SF transistor 201 is connected to a terminal bus 231. FIG. 2 also includes a potential diagram 206 of the simplified device 200, and the potential diagram 206 illustrates a charge transfer flow from the photodiode 205 into a FD node 203 and finally into a terminal 204, doped with an N+-type impurity, during charge reset. A pixel is formed in a P-type silicon substrate 219 that has pixel isolation trenches 207 formed in the P-type silicon substrate 219 and filled by an oxide 210. Another oxide layer 218 is grown on a top portion of the substrate 219 that isolates a gate 211 of a charge transfer transistor and a gate 212 of a reset transistor from the substrate 219. The gates 211 and 212 of the charge transfer transistor and the reset transistor are connected to the respective horizontal bus lines 213 and 214 that supply a required bias to the gates 211 and 212. Gate control signals Tx and Rx of the charge transfer transistor and the reset transistor are transferred through the horizontal bus lines 213 and 214, respectively. The pinned photodiode 205 is formed in the substrate 219 by a P+-type diffusion region 208 that extends along a sidewall of each of the trenches 207 all the way to the P-type substrate 219 and by an N-type diffusion region 209. It is also possible to use more sophisticated doping profiles as is well known to those skilled in this art. The charge transfer transistor with the gate 211 connects the pinned photodiode 205 to the FD node 203, and the reset transistor with the gate 212 connects the FD node 203 to the terminal 204 doped with the N+-type impurity.
As can be seen from the potential diagram 206 that is located under the cross-sectional view of the simplified device 200 in FIG. 2, potential levels of the potential diagram 206 correspond to each device built into the substrate 219, and the pinned photodiode 205 forms a potential well that accumulates a signal charge 221 during the time when the gate 211 of the charge transfer transistor is off. The off state of the gate 211 of the charge transfer transistor is indicated in the potential diagram 216 by a potential level 222. An overflow charge (blooming current) from the potential well flows via a path 230 through the reset transistor directly to the terminal 204. When the charge transfer transistor is turned on, the potential level 222 under the charge transfer transistor changes to a potential level 223, and the signal charge 221 flows into the FD node 203. The signal charge transferred into the FD node 203 is indicated by a reference numeral 224. The signal charge 224 causes a potential level 225 of the FD node 203 to change to a new potential level 226. The new potential level 226 represents a voltage signal that is sensed by the SF transistor 201. When applying an appropriate bias, i.e., a gate control signal Sx, to a gate of the addressing transistor 202 through a bus line 215, the addressing transistor 202 is turned on and the voltage signal from the SF transistor 201 is transferred to a pixel output bus 216.
The pixel is reset by applying a single reset pulse 217 to the horizontal bus line 214 connected to the gate 212 of the reset transistor. The pixel reset changes a potential level 227 under the reset transistor to a new potential level 228, which allows the signal charge 224 to flow into the terminal 204 doped with the N+-type impurity. The terminal 204 is biased at a Vdd potential level 229, which is fixed by an external device power source and cannot change. Thus, when all the signal charge 224 is transferred to the terminal 204, the FD node 203 resumes the original potential level 225 of the FD node 203. The potential level 225 of the FD node 203 is only approximately equal to the Vdd potential level 229 due to a reset feed through from the gate 212 of the reset transistor and kTC-reset noise. It is therefore desirable to use the CDS procedure to sample both of the potential levels 225 and 226 since a true photo-generated signal is the difference between these two potential levels.
As is now clear from the potential diagram 206, a FD voltage swing is limited on a high side by the Vdd potential level 229 and on a low side by an empty pinned photodiode level 220 of the pinned photodiode 205. When too much signal accumulates in the photodiode 205, not all of the signal can be transferred into the FD node 203, which results in the lower sensitivity and increased noise. It is desirable to have a large voltage swing on the FD node 203 and thus decrease the pinned photodiode level 220, i.e., a pinning voltage level of the pinned photodiode 205. However, the low pinning voltage level results in a low photodiode charge storage capacity, thereby causing a low dynamic range (DR) and a low signal to noise ratio (SNR). Accordingly, it is necessary to find a suitable compromise between these two competing requirements. This compromise then determines an ultimate performance of the pixel that is clearly determined by the maximum Vdd potential level 229 that can be used in the sensor. To have a large Vdd potential level is a disadvantage, since the large Vdd potential level increases the sensor power consumption.